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Si5040
6.4. Transmitter Loss of Lock (LOL)
Transmitter LOL functions in different ways depending on whether the transmitter is operating in reference or
referenceless mode. By default (uselolmode Register 135, Bit 3 = 0), SQM-based LOL is used in referenceless
mode, and Frequency-based LOL is used in reference mode. However, in reference mode, either SQM or
Frequency LOL can be used by setting Register 135, Bits 2 and 3, to the appropriate values.
6.4.1. SQM LOL
When the VCO is configured to calibrate without a reference clock (VCOCAL[1:0] = 01 binary), the default values
of register 135[3:2] will cause the LOL method to be SQMLOL. Just as in the receiver (see "5.8.1. SQM LOL" on
page 24), the SQMLOL method compares an internal jitter measure to the sqmLOLThresh; however, the TX
sqmLOLThresh value must not be modified. When the internal jitter measure is greater than the sqmLOLThresh,
TXLOL is asserted. TxLOL is deasserted when the jitter measure is less than the sqmLOLThresh.
6.4.1.1. Dynamic Register Control
The dynamic control of TxLoopFAcq (Register 226) is required to ensure the locking performance of the CDR. For
all applications, it is required that TxLoopFAcq be set to 98h when TX LOL is asserted and to 00h when TX LOL is
deasserted. Only the default value and the value given above are supported for Register 226. Any read back of this
register will not necessarily return 98h. If a valid reference clock is applied at pins 13,14 and the Tx VCOCAL = x0b
(reg136[2:1]), then the dynamic register write to register 226 is not necessary.
In addition, for proper LOL performance, TxPDGainAcq (Register 205) must be written once to 0Dh after power is
applied or a SW reset is implemented. If a valid reference clock is applied at pins 13,14 and Tx VCOCAL = x0b
(reg136[2:1]) then it is not necessary to write to register 205.
6.4.2. Frequency LOL
The Si5040 supports the use of a ~622 MHz or ~155 MHz (/64 or /16) reference clock. When FREQLOL is set
(Register 135[3:2] = 10b), LOL is asserted if the recovered clock frequency deviates from the reference clock
frequency by >±1000 ppm. LOL is de-asserted if the recovered clock is within ±200 ppm of the reference clock
frequency. The reference clock frequency is selected in the ChipConfig1 register (Register 2). Refer to Figure 14
for CDR and VCO behaviors upon declaring LOL.
6.4.3. Acquisition Time Enhancement
The acquisition time for a signal applied at TD can be reduced to less than 15 ms by the following register writes:
?
?
?
Register 195 = 0100 0000 = 40h
Register 196 = 0000 0111 = 07h
Register 214 = 0011 1000 = 38h
6.4.4. LOL Interrupt
LOL may be configured to generate an interrupt. The status of the LOL interrupt bit can be read from the
TxintStatus register (Register 133). The status of LOL may also be read from the TxAlarmStatus register (Register
137). Transmitter data (TXDOUT) may be squelched on LOL. This option is configured in the TxdPathConfig
register (Register 156).
6.5. Transmitter Phase Adjust
The Si5040 transmitter supports manual sample phase adjust. The sampling point may be advanced or delayed in
time by adjusting the value loaded into the PhaseAdjust register (Register 152). The range of adjustment is
>±12 ps. Note that the transfer function from the register value to the phase adjust time is highly variable; therefore,
we only guarantee that the largest or smallest register value will achieve better than +12 ps or –12 ps, respectively.
6.6. Transmit Clock Multiplier Unit
The Si5040 transmitter incorporates a DSPLL ? -based clock multiplier unit (CMU) that attenuates the jitter on the
data recovered from the XFI interface. This makes it much easier to significantly exceed the jitter requirements for
10 Gbit SONET, Ethernet, and FibreChannel applications. The CMU is rate-adaptable across the entire range of
device operation. Selectable CMU bandwidths support adjustment of the degree of jitter filtering required for a
given application.
30
Rev. 1.3
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